Many electronic devices, especially mobile devices that are limited by battery capacity, include an off-chip, power management integrated circuit (PMIC) that is used to generate one or more power supply voltages for a main processor. PMICs may implement one or more of the following functions: voltage regulation, DC to DC conversion, battery charging, power source selection, voltage scaling, and the like. In one mode of operation, the PMIC may be used to provide different voltage levels to a device in order to save power during different types of operation. For example, a processor may be operated at a low frequency under a lower supply voltage during a first mode and a higher frequency under a higher supply voltage during a second mode.
Conventional PMICs require a feedback loop that provides a measurement of the un-gated supply voltage (CVDD) provided by the PMIC. Typical processors may provide this feedback signal by sampling one or more gated voltages on the device using an n-to-1 analog multiplexor. The analog multiplexor shorts any number of the on-chip gated voltage supplies to the feedback input of the PMIC. However, during an initial ramp-up stage of the PMIC, the supply voltage to the analog multiplexor may be below a threshold voltage and, therefore, the analog multiplexor may be uncontrollable because the incoming multiplexor control signals are driven by the ramping supply voltage. Thus, the analog multiplexor may pass-through an unknown output during the ramping stage.
FIG. 1 illustrates a conventional feedback circuit for a PMIC, in accordance with the prior art. The feedback circuit includes a PMIC 50 located off-chip and an analog multiplexor 30 and a plurality of voltage domains (VDn) 10 located on-chip. An input to the PMIC 50 (i.e., V_In) and an output of the PMIC 50 (i.e., V_Out) are coupled to pins on the chip such as solder bumps on a bottom of the package that contains the integrate circuit device. The V_Out signal is the un-gated power supply for the device (CVDD) and the V_In signal is a voltage feedback signal that enables the PMIC 50 to adjust the V_Out signal to meet a target voltage. Each of the voltage domains (i.e., VD1 10(1), VD2 10(2), etc.) are supplied with a gated supply voltage (V_n) that is shorted to CVDD through a switch (VSel_n). The analog multiplexor 30 is coupled to CVDD as a supply voltage and is controlled with one or more control signals (SELn . . . 0).
As shown in FIG. 1, the analog multiplexor 30 receives a supply voltage from CVDD and the control signals are driven via CVDD. However, as explained above, when CVDD is ramping up and below a threshold voltage, the analog multiplexor may have unknown operation. One solution to this problem is to provide the analog multiplexor with an independent supply voltage. The requirements of this supply voltage are that the independent supply voltage is brought up and stabilized before CVDD begins ramping up and only goes down after CVDD goes down. The independent supply voltage would also have to be greater than or equal to CVDD at all times in order to ensure that the n-doped wells of the PMOS (p-type metal oxide semiconductor) devices within the analog multiplexor are not negatively biased. In addition, the output of the analog multiplexor 30 would be required to have electrostatic discharge (ESD) protection such as an ESD clamp, which takes up valuable die real estate. Furthermore, a new solder bump would need to be allocated to bring this new voltage on-chip, which could reduce the integrity of the core supply/ground bump grid of the device. Thus, there is a need for addressing these issues and/or other issues associated with the prior art.